IISc

Profile
Personal Information
Expertise Information
Experience
Education Qualification
Honours and Awards
Patents
Publications

Academic Identity

Scopus Id 35119398300
Google Scholar Id zmJtC_AAAAAJ

Vidwan-ID : 54781

Edit Profile

Invalid Username or Email And Password!

Login

Forgot password ?

Dr Mayank Shrivastava
Associate Professor
Indian Institute of Science, Bangalore

Publications 2008 - 2024

Publications

107

Journal Articles
1

Book Chapter
67

Conference
Proceedings
1

Review
1

Other
6
6
122

Citations / H-Index

1559 Citations

20 h-index

1683 Citations

Altmetrics

111

141

330

Google Scholar

Co-author Network

Years

{{ year.name}}

Expertise

Electrical and Electronic Engineering

Beyond CMOS Devices, 2D And 1D Materials, Nanoscale Device Design And Modeling, ESD Devices And Circuits, LDMOS And Demos Device Design, Device-Circuit Co-Design And Electrothermal Modeling.

Personal Information

Dr Mayank Shrivastava

Male

Electronic Systems Engineering Indian Institute of Science

, Karnataka, India - 560012

http://www.dese.iisc.ernet.in/ese/index.php/facultys/mayank-shrivastava

Experience

2019 - Present

Associate Professor

Electronic Systems Engineering

Indian Institute of Science, Bangalore
2013 - 2018

Assistant Professor

Electronic Systems Engineering

Indian Institute of Science, Bangalore

Qualification

2010

Ph.D

Indian Institute of Technology, Bombay
2006

BE

Rajiv Gandhi Technical University

Honours and Awards

2018

Young Scientist Platinum Jubilee Award

National Academy of Sciences, India

2018

INSA Young Scientist Award

Indian National Science Academy

2018

Engineening Innovator Entrepreneur Award

Indian National Science Academy

2018

Young Scientist Platinum Jubilee Award

National Academy of Sciences, India

2018

INSA Young Scientist Award

Indian National Science Academy

2018

Engineening Innovator Entrepreneur Award

Indian National Science Academy

Read Less

Patents

ENHANCEMENT MODE HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)

Shrivastava Mayank,Bangalore,IN | Dutta Gupta Sayak,Bangalore,IN | Soni Ankit,Bangalore,IN | Raghavan Srinivasan,Bangalore,IN | Bhat Navakanta,Bangalore,IN

Patent No. US20190067440A1
Published

Filed 2018-08-28
Published 2019-02-28

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith | SONI Ankit | SHRIVASTAVA Mayank | RAGHAVAN Srinivasan | BHAT Navakant

Patent No. IN310947B
Published

Filed 2017-07-07
Published 2019-04-12

BURIED CHANNEL NORMALLY-OFF GAN HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith | SONI Ankit | SHRIVASTAVA Mayank | RAGHAVAN Srinivasan | BHAT Navakant

Patent No. IN201741024073A
Published

Filed 2017-07-07
Published 2018-07-27

Shrivastava Mayank,Bangalore,IN | Dutta Gupta Sayak,Bangalore,IN | Soni Ankit,Bangalore,IN | Raghavan Srinivasan,Bangalore,IN | Bhat Navakanta,Bangalore,IN

INDIAN INSTITUTE OF SCIENCE,Bangalore,IN | INDIAN INST SCIENT

Patent No. US20190067440A1
Published

Filed 2018-08-28
Published 2019-02-28

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith | SONI Ankit | SHRIVASTAVA Mayank | RAGHAVAN Srinivasan | BHAT Navakant

INDIAN INSTITUTE OF SCIENCE

Patent No. IN310947B
Published

Filed 2017-07-07
Published 2019-04-12

BURIED CHANNEL NORMALLY-OFF GAN HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith | SONI Ankit | SHRIVASTAVA Mayank | RAGHAVAN Srinivasan | BHAT Navakant

INDIAN INSTITUTE OF SCIENCE

Patent No. IN201741024073A
Published

Filed 2017-07-07
Published 2018-07-27

TRANSISTOR À HAUTE MOBILITÉ D'ÉLECTRONS (HEMT) À JONCTION RESURF | HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith,IN | SONI Ankit,IN | SHRIVASTAVA Mayank,IN | RAGHAVAN Srinivasan,IN | BHAT Navakant,IN

INDIAN INSTITUTE OF SCIENCE,IN

Patent No. WO2019008603A1
Published

Filed 2018-07-06
Published 2019-01-10

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith,Karnataka Bangalore,IN | SONI Ankit,Karnataka Bangalore,IN | SHRIVASTAVA Mayank,Karnataka Bangalore,IN | RAGHAVAN Srinivasan,Karnataka Bangalore,IN | BHAT Navakant,Karnataka Bangalore,IN

Indian Institute of Science,Kamataka Bangalore,IN | INDIAN INST SCIENT

Patent No. US20200227543A1
Published

Filed 2020-01-07
Published 2020-07-16

METHODS OF MANUFACTURING 2-DIMENTIONAL SEMICONDUCTOR TRANSISTORS

ANSH | KURUVA H | SHRIVASTAVA Mayank

Indian Institute of Science

Patent No. IN201741033081A
Published

Filed 2017-09-19
Published 2019-03-22

DUAL FIN SILICON CONTROLLED RECTIFIER (SCR) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE

PAUL Milova | SHRIVASTAVA Mayank | KUMAR B. Sampath | RUSS Christian | GOSSNER Harald

INDIAN INSTITUTE OF SCIENCE

Patent No. IN201741003771A
Published

Filed 2017-02-01
Published 2018-08-03

Dual fin silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection device

Paul Milova,Bangalore,IN | Shrivastava Mayank,Bangalore,IN | Kumar B. Sampath,Bangalore,IN | Russ Christian,Diedorf,DE | Gossner Harald,Riemerling,DE

INDIAN INSTITUTE OF SCIENCE,Bangalore,IN | INDIAN INSTITUTE OF SCIENCE,Bangalore, Karnataka,IN | INDIAN INST SCIENT

Patent No. US10629586B2
Published

Filed 2018-01-30
Published 2020-04-21

DUAL FIN SILICON CONTROLLED RECTIFIER (SCR) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE

PAUL Milova,Bangalore,IN | SHRIVASTAVA Mayank,Bangalore,IN | KUMAR B. Sampath,Bangalore,IN | RUSS Christian,Diedorf,DE | GOSSNER Harald,Riemerling,DE

INDIAN INSTITUTE OF SCIENCE,Bangalore,IN | INDIAN INST SCIENT

Patent No. US20190013310A1
Published

Filed 2018-01-30
Published 2019-01-10

RECESS GATE SUPERJUNCTION HIGH-ELECTRON-MOBILITY TRANSISTOR (HEMT)

SHRIVASTAVA Mayank

Indian Institute of Science

Patent No. IN201741024695A
Published

Filed 2017-07-12
Published 2019-01-18

DRAIN EXTENDED TUNNEL FIELD EFFECT TRANSISTOR

SHRIVASTAVA Mayank

Indian Institute of Science

Patent No. IN201641006497A
Published

Filed 2016-02-25
Published 2017-09-01

MINIATURIZED, HIGH POWER DENSITY POWER ELECTRONIC SYSTEM ON A CHIP

SHRIVASTAVA Mayank

Indian Institute of Science

Patent No. IN201501355I4
Published

Filed 2015-03-19
Published 2016-09-30

FIN ENABLED AREA SCALED TUNNEL FIELD EFFECT TRANSISTER

SHRIVASTAVA Mayank | HEMANJANEYULU Kuruva

Indian Institute of Science

Patent No. IN201502625I4
Published

Filed 2015-05-26
Published 2016-12-02

DOPING AND TRAP PROFILE ENGINEERING IN GAN BUFFER TO MAXIMIZE ALGAN/GAN HEMT EPI STACK BREAKDOWN VOLTAGE

SHRIVASTAVA Mayank | JOSHI Vipin

INDIAN INSTITUTE OF SCIENCE

Patent No. IN201841020899A
Published

Filed 2018-06-05
Published 2019-12-06

A FIELD EFFECT TRANSISTOR (FET) WITH IMPROVED FAILURE THRESHOLD

SHRIVASTAVA Mayank | KRANTHI Nagothu Karmel | HEMANJANEYULU Kuruva

Indian Institute of Science

Patent No. IN201741025123A
Published

Filed 2017-07-14
Published 2019-01-18

FINFET SCR WITH SCR IMPLANT UNDER ANODE AND CATHODE JUNCTIONS

SHRIVASTAVA Mayank | PAUL Milova | GOSSNER Harald

Indian Institute of Science

Patent No. IN201741006746A
Published

Filed 2017-02-25
Published 2018-08-31

ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES FOR ESD ROBUSTNESS AND LATCH-UP IMMUNITY

SHRIVASTAVA Mayank | PAUL Milova | GOSSNER Haraldz

Indian Institute of Science

Patent No. IN201741006745A
Published

Filed 2017-02-25
Published 2018-08-31

NON-PLANAR ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES WITH NANO HEAT SINKS

SHRIVASTAVA Mayank | PAUL Milova | RUSS Christian | GOSSNER Harald

INDIAN INSTITUTE OF SCIENCE

Patent No. IN201741003773A
Published

Filed 2017-02-01
Published 2018-08-03

LOW TRIGGER AND HOLDING VOLTAGE SILICON CONTROLLED RECTIFIER (SCR) FOR NON-PLANAR TECHNOLOGIES

SHRIVASTAVA Mayank | PAUL Milova | RUSS Christian | GOSSNER Harald

INDIAN INSTITUTE OF SCIENCE

Patent No. IN201741003772A
Published

Filed 2017-02-01
Published 2018-08-03

High-electron-mobility transistor (HEMT)

Shrivastava Mayank,Bangalore,IN

INDIAN INSTITUTE OF TECHNOLOGY,Bangalore,IN | INDIAN INSTITUTE OF SCIENCE,Bangalore,IN | INDIAN INST SCIENT | INDIAN INSTITUTE OF TECH

Patent No. US10553712B2
Published

Filed 2018-07-11
Published 2020-02-04

A High-electron-mobility transistor (HEMT)

SHRIVASTAVA MAYANK,BANGALORE,IN

INDIAN INSTITUTE OF SCIENCE | INDIAN INSTITUTE OF SCIENCE,Bangalore,IN | INDIAN INST SCIENT

Patent No. US20190081164A1
Published

Filed 2018-07-11
Published 2019-03-14

DOPING AND TRAP PROFILE ENGINEERING IN GaN BUFFER TO MAXIMIZE AlGaN/GaN HEMT EPI STACK BREAKDOWN VOLTAGE

SHRIVASTAVA Mayank,Bangalore,IN | Joshi Vipin,Bangalore,IN

Indian Institute of Science,Bangalore,IN | INDIAN INST SCIENT

Patent No. US20190371930A1
Published

Filed 2019-06-04
Published 2019-12-05

FinFET SCR with SCR implant under anode and cathode junctions

Shrivastava Mayank,Bangalore,IN | Paul Milova,Bangalore,IN | Gossner Harald,Riemerling,DE

INDIAN INSTITUTE OF SCIENCE,Karnataka, Bangalore,IN | Indian Institute of Science,Bangalore,IN | INDIAN INST SCIENT

Patent No. US10535762B2
Published

Filed 2018-02-19
Published 2020-01-14

Semiconductor devices and methods to enhance electrostatic discharge (ESD) robustness, latch-up, and hot carrier immunity

Shrivastava Mayank,Bangalore,IN | Paul Milova,Bangalore,IN | Gossner Harald,Riemerling,DE

INDIAN INSTITUTE OF SCIENCE,Karnataka, Bangalore,IN | Indian Institute of Science,Bangalore,IN | INDIAN INST SCIENT

Patent No. US10483258B2
Published

Filed 2018-02-19
Published 2019-11-19

FINFET SCR WITH SCR IMPLANT UNDER ANODE AND CATHODE JUNCTIONS

Shrivastava Mayank,Bangalore,IN | Paul Milova,Bangalore,IN | Gossner Harald,Riemerling,DE

Indian Institute of Science,Bangalore,IN | INDIAN INST SCIENT

Patent No. US20180248025A1
Published

Filed 2018-02-19
Published 2018-08-30

SEMICONDUCTOR DEVICES AND METHODS TO ENHANCE ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS, LATCH-UP, AND HOT CARRIER IMMUNITY

Shrivastava Mayank,Bangalore,IN | Paul Milova,Bangalore,IN | Gossner Harald,Riemerling,DE

Indian Institute of Science,Bangalore,IN | INDIAN INST SCIENT

Patent No. US20180247929A1
Published

Filed 2018-02-19
Published 2018-08-30

Non-planar electrostatic discharge (ESD) protection devices with nano heat sinks

Shrivastava Mayank,Bangalore,IN | Paul Milova,Bangalore,IN | Russ Christian,Diedorf,DE | Gossner Harald,Riemerling,DE

INDIAN INSTITUTE OF SCIENCE,Bangalore,IN | INDIAN INSTITUTE OF SCIENCE,Bangalore, Karnataka,IN | INDIAN INST SCIENT

Patent No. US10319662B2
Published

Filed 2018-01-30
Published 2019-06-11

Low trigger and holding voltage silicon controlled rectifier (SCR) for non-planar technologies

Shrivastava Mayank,Bangalore,IN | Paul Milova,Bangalore,IN | Russ Christian,Diedorf,DE | Gossner Harald,Riemerling,DE

INDIAN INST SCIENT | INDIAN INSTITUTE OF SCIENCE,Bangalore,IN

Patent No. US10211200B2
Published

Filed 2018-01-30
Published 2019-02-19

NON-PLANAR ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES WITH NANO HEAT SINKS

SHRIVASTAVA Mayank,Bangalore,IN | PAUL Milova,Bangalore,IN | RUSS Christian,Diedorf,DE | GOSSNER Harald,Riemerling,DE

INDIAN INSTITUTE OF SCIENCE,Bangalore,IN | INDIAN INST SCIENT

Patent No. US20180226317A1
Published

Filed 2018-01-30
Published 2018-08-09

LOW TRIGGER AND HOLDING VOLTAGE SILICON CONTROLLED RECTIFIER (SCR) FOR NON-PLANAR TECHNOLOGIES

SHRIVASTAVA Mayank,Bangalore,IN | PAUL Milova,Bangalore,IN | RUSS Christian,Diedorf,DE | GOSSNER Harald,Riemerling,DE

INDIAN INST SCIENT | INDIAN INSTITUTE OF SCIENCE,Bangalore,IN

Patent No. US20180219007A1
Published

Filed 2018-01-30
Published 2018-08-02

DRAIN EXTENDED TUNNEL FIELD EFFECT TRANSISTOR

MAYANK SHRIVASTAVA

INDIAN INSTITUTE OF SCIENCE

Patent No. US20210119044B2
Published

Filed 2017-02-23
Published 2021-04-22

SEMICONDUCTOR DEVICE AND METHODS TO ENHANCE ELECTROSTATIC DISCHARGE (ESD) ROBUSTNESS, lLATCH-UP,AND HOT CARRIER IMMUNITY

MAYANK SHRIVASTAVA|MILOVA PAUL|HARALD GOSSNER

INDIAN INSTITUTE OF SCIENCE

Patent No. US10483258B2
Published

Filed 2018-02-19
Published 2019-11-19

ENHANCEMENT MODE HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)

MAYANK SHRIVASTAVA|SAYAK DUTTA GUPTA|ANKIT SONI|SRINIVASAN RAGHAVAN|NAVAKANTA BHAT

INDIAN INSTITUTE OF SCIENCE

Patent No. IN201741030570
Published

Filed 2017-08-29
Published 2019-03-01

Read Less

Publications (177)

Year : Oldest
Year : Newest
Publication Title : Ascending
Publication Title : Descending
Publication Type : Ascending
Publication Type : Descending

Academic Identity

Vidwan-ID : 54781

Dr Mayank Shrivastava

Publications 2008 - 2024

Publications

Journal Articles

Book Chapter

Conference Proceedings

Review

Other

Citations / H-Index

Altmetrics

Google Scholar

Co-author Network

Co-author - 459

Expertise

Electrical and Electronic Engineering

Beyond CMOS Devices, 2D And 1D Materials, Nanoscale Device Design And Modeling, ESD Devices And Circuits, LDMOS And Demos Device Design, Device-Circuit Co-Design And Electrothermal Modeling.

Personal Information

Dr Mayank Shrivastava

Experience

Associate Professor

Assistant Professor

Qualification

Ph.D

BE

Honours and Awards

Young Scientist Platinum Jubilee Award

INSA Young Scientist Award

Engineening Innovator Entrepreneur Award

Young Scientist Platinum Jubilee Award

INSA Young Scientist Award

Engineening Innovator Entrepreneur Award

Patents

ENHANCEMENT MODE HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)

Shrivastava Mayank,Bangalore,IN | Dutta Gupta Sayak,Bangalore,IN | Soni Ankit,Bangalore,IN | Raghavan Srinivasan,Bangalore,IN | Bhat Navakanta,Bangalore,IN

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith | SONI Ankit | SHRIVASTAVA Mayank | RAGHAVAN Srinivasan | BHAT Navakant

BURIED CHANNEL NORMALLY-OFF GAN HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith | SONI Ankit | SHRIVASTAVA Mayank | RAGHAVAN Srinivasan | BHAT Navakant

ENHANCEMENT MODE HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)

Shrivastava Mayank,Bangalore,IN | Dutta Gupta Sayak,Bangalore,IN | Soni Ankit,Bangalore,IN | Raghavan Srinivasan,Bangalore,IN | Bhat Navakanta,Bangalore,IN

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith | SONI Ankit | SHRIVASTAVA Mayank | RAGHAVAN Srinivasan | BHAT Navakant

BURIED CHANNEL NORMALLY-OFF GAN HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith | SONI Ankit | SHRIVASTAVA Mayank | RAGHAVAN Srinivasan | BHAT Navakant

TRANSISTOR À HAUTE MOBILITÉ D'ÉLECTRONS (HEMT) À JONCTION RESURF | HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith,IN | SONI Ankit,IN | SHRIVASTAVA Mayank,IN | RAGHAVAN Srinivasan,IN | BHAT Navakant,IN

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION

SOMAN Rohith,Karnataka Bangalore,IN | SONI Ankit,Karnataka Bangalore,IN | SHRIVASTAVA Mayank,Karnataka Bangalore,IN | RAGHAVAN Srinivasan,Karnataka Bangalore,IN | BHAT Navakant,Karnataka Bangalore,IN

METHODS OF MANUFACTURING 2-DIMENTIONAL SEMICONDUCTOR TRANSISTORS

ANSH | KURUVA H | SHRIVASTAVA Mayank

DUAL FIN SILICON CONTROLLED RECTIFIER (SCR) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE

PAUL Milova | SHRIVASTAVA Mayank | KUMAR B. Sampath | RUSS Christian | GOSSNER Harald

Dual fin silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection device

Paul Milova,Bangalore,IN | Shrivastava Mayank,Bangalore,IN | Kumar B. Sampath,Bangalore,IN | Russ Christian,Diedorf,DE | Gossner Harald,Riemerling,DE

DUAL FIN SILICON CONTROLLED RECTIFIER (SCR) ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE

PAUL Milova,Bangalore,IN | SHRIVASTAVA Mayank,Bangalore,IN | KUMAR B. Sampath,Bangalore,IN | RUSS Christian,Diedorf,DE | GOSSNER Harald,Riemerling,DE

RECESS GATE SUPERJUNCTION HIGH-ELECTRON-MOBILITY TRANSISTOR (HEMT)

SHRIVASTAVA Mayank

DRAIN EXTENDED TUNNEL FIELD EFFECT TRANSISTOR

SHRIVASTAVA Mayank

MINIATURIZED, HIGH POWER DENSITY POWER ELECTRONIC SYSTEM ON A CHIP

SHRIVASTAVA Mayank

FIN ENABLED AREA SCALED TUNNEL FIELD EFFECT TRANSISTER

SHRIVASTAVA Mayank | HEMANJANEYULU Kuruva

DOPING AND TRAP PROFILE ENGINEERING IN GAN BUFFER TO MAXIMIZE ALGAN/GAN HEMT EPI STACK BREAKDOWN VOLTAGE

SHRIVASTAVA Mayank | JOSHI Vipin

A FIELD EFFECT TRANSISTOR (FET) WITH IMPROVED FAILURE THRESHOLD

SHRIVASTAVA Mayank | KRANTHI Nagothu Karmel | HEMANJANEYULU Kuruva

FINFET SCR WITH SCR IMPLANT UNDER ANODE AND CATHODE JUNCTIONS

SHRIVASTAVA Mayank | PAUL Milova | GOSSNER Harald

ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES FOR ESD ROBUSTNESS AND LATCH-UP IMMUNITY

SHRIVASTAVA Mayank | PAUL Milova | GOSSNER Haraldz

NON-PLANAR ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES WITH NANO HEAT SINKS

SHRIVASTAVA Mayank | PAUL Milova | RUSS Christian | GOSSNER Harald

LOW TRIGGER AND HOLDING VOLTAGE SILICON CONTROLLED RECTIFIER (SCR) FOR NON-PLANAR TECHNOLOGIES

SHRIVASTAVA Mayank | PAUL Milova | RUSS Christian | GOSSNER Harald

High-electron-mobility transistor (HEMT)

Shrivastava Mayank,Bangalore,IN

Conference
Proceedings